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Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs

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Abstract

In this work HLS is used for designing a parametric optical flow Hierarchical algorithm in FPGAs. The algorithm that is designed is the Hierarchical (pyramid) Horn and Schunck algorithm, both a multi-rate and multi-level (multi-scale) algorithm, which achieves larger motion displacement detection than the mono-scale ones. With the help of HLS, we parametrize our design in terms of the levels of the pyramid, the iteration factor and the number of pixels computed per clock. We are reusing the same resources in each level of the pyramid to keep the usage of DSPs and RAM low. We perform a design space exploration of the algorithm and we show that our fastest design achieves a throughput of 461 Mpixel/s in a 2048×2048 resolution pixel image.
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Dates and versions

hal-03691829 , version 1 (09-06-2022)

Identifiers

  • HAL Id : hal-03691829 , version 1

Cite

Ilias Bournias, Roselyne Chotin, Lionel Lacassagne. Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs. IEEE International Symposium on Circuits and Systems (ISCAS 2022), May 2022, Austin, TX, United States. ⟨hal-03691829⟩
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