VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005)

Abstract : This paper presents an innovating methodology for fast and easy design of Asynchronous Network-on-Chips (ANoCs) dedicated to GALS systems. A topology-independent building-block approach permits to design modular and scalable ANoCs with low-power and low-complexity requirements. A crossbar generator is added to the existing design flow for fast system architecture exploration. A multi-clock FPGA allows a fast prototyping of complex ANoC-centric GALS systems. A demonstrative platform is implemented onto an Altera Stratix FPGA. It includes synchronous standard IP cores and asynchronous modules connected through an asynchronous 6x6 crossbar. Results about communication costs across the Asynchronous NoC and synchronous/asynchronous interfaces are reported.
Type de document :
Chapitre d'ouvrage
VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer, pp.195-207, 2007
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https://hal-emse.ccsd.cnrs.fr/emse-00429856
Contributeur : Sabine Salmeron <>
Soumis le : mercredi 4 novembre 2009 - 16:50:11
Dernière modification le : jeudi 11 janvier 2018 - 06:15:43

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  • HAL Id : emse-00429856, version 1

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Jérôme Quartana, Laurent Fesquet, Marc Renaudin. VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005). VLSI-SOC: From Systems to Chips, (selected contributions from VLSI-SoC 2005), Springer, pp.195-207, 2007. 〈emse-00429856〉

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