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Conference Papers Year : 2006

Integrated Evaluation Platform for Secured Devices


In this paper, we describe the structure of a FPGA smart card emulator. The aim of such an emulator is to improve the behaviour of the whole architecture when faults occur. Within this card, an embedded Advanced Encryption Standard (AES) protected against DFA is inserted as well as a fault injection block. We also present the microprocessor core which controls the whole card.
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Dates and versions

emse-00481458 , version 1 (09-02-2016)


  • HAL Id : emse-00481458 , version 1


Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Bruno Robisson, et al.. Integrated Evaluation Platform for Secured Devices. Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. p214-220. ⟨emse-00481458⟩
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