Integrated Evaluation Platform for Secured Devices - Mines Saint-Étienne Access content directly
Conference Papers Year : 2006

Integrated Evaluation Platform for Secured Devices

Abstract

In this paper, we describe the structure of a FPGA smart card emulator. The aim of such an emulator is to improve the behaviour of the whole architecture when faults occur. Within this card, an embedded Advanced Encryption Standard (AES) protected against DFA is inserted as well as a fault injection block. We also present the microprocessor core which controls the whole card.
Fichier principal
Vignette du fichier
060523_SESAM_recosoc06.pdf (527.25 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

emse-00481458 , version 1 (09-02-2016)

Identifiers

  • HAL Id : emse-00481458 , version 1

Cite

Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Bruno Robisson, et al.. Integrated Evaluation Platform for Secured Devices. Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. p214-220. ⟨emse-00481458⟩
239 View
234 Download

Share

Gmail Facebook X LinkedIn More