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Integrated Evaluation Platform for Secured Devices

Abstract : In this paper, we describe the structure of a FPGA smart card emulator. The aim of such an emulator is to improve the behaviour of the whole architecture when faults occur. Within this card, an embedded Advanced Encryption Standard (AES) protected against DFA is inserted as well as a fault injection block. We also present the microprocessor core which controls the whole card.
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https://hal-emse.ccsd.cnrs.fr/emse-00481458
Contributor : Bruno Robisson <>
Submitted on : Tuesday, February 9, 2016 - 10:13:54 PM
Last modification on : Wednesday, June 24, 2020 - 4:18:23 PM
Document(s) archivé(s) le : Saturday, November 12, 2016 - 3:52:54 PM

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  • HAL Id : emse-00481458, version 1

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Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Bruno Robisson, et al.. Integrated Evaluation Platform for Secured Devices. Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. p214-220. ⟨emse-00481458⟩

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