Low-cost fault tolerance on the ALU in simple pipelined processors

Abstract : For security issues in portable applications such as smart card, various proposed techniques can be applied to harden the ALU against fault attacks. Among others, time redundancy is a good candidate to offer a low hardware cost. The main disadvantage of this scheme is high extra time due to the recomputation. However, this impact can be considerably reduced by exploiting idle hardware in the ALU. In this paper, we will show that applying this scheme in a simple processor-based smart card can reduce down to 30%-20% of extra time and requires a reasonable hardware overhead about 20.4%.
Type de document :
Communication dans un congrès
DDECS 2010 - 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2010, Vienne, Austria. IEEE, pp.28-31, 2010, 〈10.1109/DDECS.2010.5491822〉
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https://hal-emse.ccsd.cnrs.fr/emse-00481515
Contributeur : Bruno Robisson <>
Soumis le : jeudi 6 mai 2010 - 17:12:36
Dernière modification le : vendredi 16 novembre 2018 - 02:05:12

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Minh-Huu Nguyen, Bruno Robisson, Michel Agoyan, Nathalie Drach. Low-cost fault tolerance on the ALU in simple pipelined processors. DDECS 2010 - 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2010, Vienne, Austria. IEEE, pp.28-31, 2010, 〈10.1109/DDECS.2010.5491822〉. 〈emse-00481515〉

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