When Clocks Fail: On Critical Paths and Clock Faults

Abstract : Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order. This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles. We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack).
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Communication dans un congrès
Dieter Gollmann; Jean-Louis Lanet; Julien Iguchi-Cartigny. 9th IFIP WG 8.8/11.2 International Conference on Smart Card Research and Advanced Applications (CARDIS), Apr 2010, Passau, Germany. Springer, Lecture Notes in Computer Science, LNCS-6035, pp.182-193, 2010, Smart Card Research and Advanced Application. 〈10.1007/978-3-642-12510-2_13〉
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https://hal-emse.ccsd.cnrs.fr/emse-00505344
Contributeur : Assia Tria <>
Soumis le : vendredi 23 juillet 2010 - 13:53:17
Dernière modification le : samedi 21 avril 2018 - 01:15:54

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Michel Agoyan, Jean-Max Dutertre, David Naccache, Bruno Robisson, Assia Tria. When Clocks Fail: On Critical Paths and Clock Faults. Dieter Gollmann; Jean-Louis Lanet; Julien Iguchi-Cartigny. 9th IFIP WG 8.8/11.2 International Conference on Smart Card Research and Advanced Applications (CARDIS), Apr 2010, Passau, Germany. Springer, Lecture Notes in Computer Science, LNCS-6035, pp.182-193, 2010, Smart Card Research and Advanced Application. 〈10.1007/978-3-642-12510-2_13〉. 〈emse-00505344〉

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