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Conference Papers Year : 2010

When Clocks Fail: On Critical Paths and Clock Faults

Abstract

Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order. This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles. We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack).

Dates and versions

emse-00505344 , version 1 (23-07-2010)

Identifiers

Cite

Michel Agoyan, Jean-Max Dutertre, David Naccache, Bruno Robisson, Assia Tria. When Clocks Fail: On Critical Paths and Clock Faults. 9th IFIP WG 8.8/11.2 International Conference on Smart Card Research and Advanced Applications (CARDIS), Apr 2010, Passau, Germany. pp.182-193, ⟨10.1007/978-3-642-12510-2_13⟩. ⟨emse-00505344⟩
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