M. Agoyan, J. Dutertre, D. Naccache, B. Robisson, and A. Tria, When Clocks Fail: On Critical Paths and Clock Faults, Proceedings of the 9 th Smart-card Research and Advanced Application Conference (CARDIS'10), pp.182-193, 2010.
DOI : 10.1007/978-3-642-12510-2_13

URL : https://hal.archives-ouvertes.fr/emse-00505344

M. Akkar and C. Giraud, An Implementation of DES and AES, Secure against Some Attacks, Proceedings of the 3rd International Workshop on Cryptographic Hardware and Embedded Systems (CHES'01, pp.309-318, 2001.
DOI : 10.1007/3-540-44709-1_26

J. Ambrose, R. Ragel, S. Parameswaran, and A. Ignjatovic, Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks, IET Computers & Digital Techniques, vol.5, issue.1, pp.1-15, 2011.
DOI : 10.1049/iet-cdt.2009.0097

R. Anderson and M. Kuhn, Low cost attacks on tamper resistant devices, Security Protocols 5th International Workshop, pp.125-136, 1997.
DOI : 10.1007/BFb0028165

R. P. Bastos, Y. Monnet, G. Sicard, F. L. Kastensmidt, M. Renaudin et al., Comparing transient-fault effects on synchronous and on asynchronous circuits, 2009 15th IEEE International On-Line Testing Symposium, pp.29-34, 2009.
DOI : 10.1109/IOLTS.2009.5195979

URL : https://hal.archives-ouvertes.fr/hal-00419061

G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, and V. Piuri, A parity code based fault detection for an implementation of the Advanced Encryption Standard, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings., pp.51-59, 2002.
DOI : 10.1109/DFTVS.2002.1173501

E. Biham and A. Shamir, Differential fault analysis of secret key cryptosystems, Proceedings of the 17 th International Advances in Cryptology Conference ? CRYPTO'97 , no. 1294 in LNCS, pp.513-525, 1997.
DOI : 10.1007/BFb0052259

E. Brier, C. Clavier, and F. Olivier, Correlation Power Analysis with a Leakage Model, Proceedings of the Workshop on Cryptographic Hardware and Embedded Systmes, pp.16-29, 2004.
DOI : 10.1007/978-3-540-28632-5_2

Z. Chen, A. Sinha, and P. Schaumont, Implementing virtual secure circuit using a custom-instruction approach, Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems, CASES '10, pp.57-66, 2010.
DOI : 10.1145/1878921.1878933

H. Choukri and M. Tunstall, Round Reduction Using Faults, 2 nd Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 05), pp.13-24, 2005.

J. Dhem, F. Koene, P. Leroux, P. Mestré, J. Quisquater et al., A Practical Implementation of the Timing Attack, Proceedings of the 3 rd Smart-card Research and Advanced Application Conference (CARDIS'98), pp.167-182, 1998.
DOI : 10.1007/10721064_15

J. J. Fournier, S. Moore, H. Li, R. Mullins, and G. Taylor, Security Evaluation of Asynchronous Circuits, Proceedings of the 5th International Workshop on Cryptographic Hardware and Embedded Systems (CHES'03 no. 2779 in LNCS, pp.137-151, 2003.
DOI : 10.1007/978-3-540-45238-6_12

K. Gandolfi, C. Mourtel, and F. Olivier, Electromagnetic Analyis: Concrete Results, Proceedings of the 3rd International Workshop on Cryptographic Hardware and Embedded Systems (CHES'01, pp.251-261, 2001.
DOI : 10.1007/3-540-44709-1_21

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

B. Gierlichs, L. Batina, P. Tuyls, and B. Preneel, Mutual Information Analysis, Cryptographic Hardware and Embedded Systems -CHES 2008, pp.426-442, 2008.
DOI : 10.1007/978-3-540-85053-3_27

C. Giraud, DFA on AES, Advanced Encryption Standard -AES, pp.27-41, 2005.
DOI : 10.1007/11506447_4

S. Guilley, P. Hoogvorst, Y. Mathieu, and R. Pacalet, The ???Backend Duplication??? Method, CHES'05, pp.383-397, 2005.
DOI : 10.1007/11545262_28

S. Guilley, L. Sauvage, F. Flament, V. Vong, P. Hoogvorst et al., Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics, IEEE Transactions on Computers, vol.59, issue.9, pp.59-1250, 2010.
DOI : 10.1109/TC.2010.104

M. Joye, P. Manet, and J. Rigaud, Strengthening hardware AES implementations against fault attacks, IET Information Security, vol.1, issue.3, pp.106-110, 2007.
DOI : 10.1049/iet-ifs:20060163

M. G. Karpovsky, K. J. Kulikowski, and A. Taubin, Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard, International Conference on Dependable Systems and Networks, 2004, pp.93-101, 2004.
DOI : 10.1109/DSN.2004.1311880

R. Karri, G. Kuznetsov, and M. Goessel, Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers, Proceedings of the 5th International Workshop on Cryptographic Hardware and Embedded Systems (CHES'03 no. 2779 in LNCS, pp.113-124, 2003.
DOI : 10.1007/978-3-540-45238-6_10

P. Kocher, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, Proceedings of Advances in Cryptology (CRYPTO'96), pp.104-113, 1996.
DOI : 10.1007/3-540-68697-5_9

P. Kocher, J. Jaffe, and B. Jun, Differential Power Analysis, Proceedings of the 19th International Advances in Cryptology Conference (CRYPTO'99), no. 1666 in LNCS, pp.388-397, 1999.
DOI : 10.1007/3-540-48405-1_25

K. Kulikowski, A. Smirnov, and A. Taubin, Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks, Proceedings of 8th Workshop on Cryptographic Hardware and Embedded Systems (CHES'06), 2006.
DOI : 10.1007/11894063_31

S. Laabidi, Méthodologie de conception de composants intégrés protégés contre les attaques par corrélation, 2010.

T. G. Malkin, F. Standaert, and M. Yung, A Comparative Cost/Security Analysis of Fault Attack Countermeasures, Second Workshop on Fault Detection and Tolerance in Cryptography, pp.109-123, 2005.
DOI : 10.1007/11889700_15

R. Mayer-sommer, Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards, Proceedings of the 2nd International Workshop on Cryptographic Hardware and Embedded Systems (CHES'00, pp.78-92, 1965.
DOI : 10.1007/3-540-44499-8_6

S. Moore, R. Anderson, R. Mullins, G. Taylor, and J. Fournier, Balanced self-checking asynchronous logic for smart card applications, Microprocessors and Microsystems, vol.27, issue.9, pp.421-430, 2003.
DOI : 10.1016/S0141-9331(03)00092-9

N. , S. Hash-standard, . Tech, and . Rep, FIPS PUB 180-2 , Federal Information Processing Standards, Cryptographic libraries for OpenSSL, 2000.

G. Piret and J. Quisquater, A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad, Proceedings of the 5th International Workshop on Cryptographic Hardware and Embedded Systems (CHES'03, pp.77-88, 2003.
DOI : 10.1007/978-3-540-45238-6_7

J. Quisquater and D. Samyde, Electromagnetic Analysis (EMA): Measures and coutermeasures for smart cards, Smart Card Programming and Security (e-smart, LNCS, pp.200-210, 2001.

R. L. Rivest, A. Shamir, and L. Adleman, A method for obtaining digital signatures and public-key cryptosystems, Communications of the ACM, vol.21, issue.2, pp.120-126, 1978.
DOI : 10.1145/359340.359342

B. Robisson and P. Manet, Differential Behavioral Analysis, CHES, pp.413-426, 2007.
DOI : 10.1007/978-3-540-74735-2_28

URL : https://hal.archives-ouvertes.fr/emse-00481468

S. Skorobogatov and R. Anderson, Optical Fault Induction Attacks, Proceedings of the Workshop on Cryptographic Hardware and Embedded Systmes no. 2533 in LNCS, pp.2-12, 2002.
DOI : 10.1007/3-540-36400-5_2

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

R. Soares, N. Calazans, V. Lomné, P. Maurine, L. Torres et al., Evaluating the robustness of secure triple track logic through prototyping, Proceedings of the twenty-first annual symposium on Integrated circuits and system design, SBCCI '08, pp.193-198, 2008.
DOI : 10.1145/1404371.1404425

URL : https://hal.archives-ouvertes.fr/lirmm-00373516

K. Tiri and I. Verbauwhede, Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology, Proceedings of the 5th International Workshop on Cryptographic Hardware and Embedded Systems (CHES'03 no. 2779 in LNCS, pp.125-136, 2003.
DOI : 10.1007/978-3-540-45238-6_11

C. Tokunaga and D. Blaauw, Secure aes engine with a local switched-capacitor current equalizer, in Solid-State Circuits Conference -Digest of Technical Papers, IEEE International, pp.64-65, 2009.

J. F. Walker and A. Alibhai-sanghrajka, Using FIB to hack security chips, European Focused Ion Beam Users Group (EFUG 2004) presentation, 2004.

S. Yen and M. Joye, Checking before output may not be enough against faultbased cryptanalysis, IEEE Transactions on Computers, vol.49, issue.9, pp.967-970, 2000.