Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key

Michel Agoyan; Sylvain Bouquet; Marion Doulcier-Verdier; Jean-Max Dutertre; Jacques Jean-Alain Fournier; Jean-Baptiste Rigaud; Bruno Robisson; Assia Tria

Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key

Michel Agoyan ^{1, 2} Sylvain Bouquet ^{1, 2} Marion Doulcier-Verdier ^{1, 2} Jean-Max Dutertre ² Jacques Jean-Alain Fournier ^{1, 2} Jean-Baptiste Rigaud ² Bruno Robisson ^{1, 2} Assia Tria ^{1, 2}

1 CMP-ENSMSE - Centre Microélectronique de Provence - Site Georges Charpak (CMP-GC)

2 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés

Abstract : The secret keys manipulated by cryptographic circuits can be extracted using fault injections associated with differential cryptanalysis techniques [1]. Such faults can be induced by different means such as lasers, voltage glitches, electromagnetic perturbations or clock skews. Several counter-measures have been proposed such as random delay insertions, circuit duplications or error correcting codes. In this paper, we focus on an AES chip in which the circuit duplication principle has been implemented to detect fault injection. We show that faults based on clock set-up time violations can nevertheless be used to defeat the implemented counter-measure.

Keywords : Dual Rail Fault attacks Advanced Encryption Standard

Document type :

Conference papers

Domain :

Computer Science [cs] / Cryptography and Security [cs.CR]

Engineering Sciences [physics] / Micro and nanotechnologies/Microelectronics

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https://hal-emse.ccsd.cnrs.fr/emse-00625679
Contributor : Jean-Max Dutertre <>
Submitted on : Friday, March 13, 2015 - 11:18:59 AM
Last modification on : Thursday, February 7, 2019 - 2:48:48 PM
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Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key

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