Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key

Michel Agoyan; Sylvain Bouquet; Marion Doulcier-Verdier; Jean-Max Dutertre; Jacques Fournier; Jean-Baptiste Rigaud; Bruno Robisson; Assia Tria

Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key

Michel Agoyan ^{1, 2} Sylvain Bouquet ^{1, 2} Marion Doulcier-Verdier ^{1, 2} Jean-Max Dutertre ² Jacques Fournier ^{1, 2} Jean-Baptiste Rigaud ² Bruno Robisson ^{1, 2} Assia Tria ^{1, 2}

1 CMP-ENSMSE - Centre Microélectronique de Provence - Site Georges Charpak (CMP-GC)

2 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés

Abstract : The secret keys manipulated by cryptographic circuits can be extracted using fault injections associated with differential cryptanalysis techniques [1]. Such faults can be induced by different means such as lasers, voltage glitches, electromagnetic perturbations or clock skews. Several counter-measures have been proposed such as random delay insertions, circuit duplications or error correcting codes. In this paper, we focus on an AES chip in which the circuit duplication principle has been implemented to detect fault injection. We show that faults based on clock set-up time violations can nevertheless be used to defeat the implemented counter-measure.

Keywords : Dual Rail Fault attacks Advanced Encryption Standard

Type de document :

Communication dans un congrès

Smart Systems Integration, Mar 2011, Dresden, Germany. pp.00, 2011

Domaine :

Informatique [cs] / Cryptographie et sécurité [cs.CR]

Sciences de l'ingénieur [physics] / Micro et nanotechnologies/Microélectronique

Liste complète des métadonnées

Littérature citée [6 références] Voir Masquer Télécharger

https://hal-emse.ccsd.cnrs.fr/emse-00625679
Contributeur : Jean-Max Dutertre <>
Soumis le : vendredi 13 mars 2015 - 11:18:59
Dernière modification le : jeudi 30 novembre 2017 - 01:19:25
Document(s) archivé(s) le : lundi 17 avril 2017 - 14:27:54

HAL_SSI2011_Design_of_a_duplic...

Fichiers produits par l'(les) auteur(s)

Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key

Fichier

Identifiants

Collections

Citation

Exporter

Métriques

411

205

Contact

Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key

Fichier

Identifiants

Collections

Citation

Exporter

Partager

Métriques

411

205

Contact