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Design and characterisation of an AES chip embedding countermeasures

Abstract : In critical communication infrastructures, hardware accelerators are often used to speed up cryptographic calculations. Their resistance to physical attacks determines how secure the overall infrastructure is. In this paper, we describe the implementation and characterisation of an AES accelerator embedding security features against physical attacks. This AES chip is implemented in HCMOS9gp 130 nm STM technology. The countermeasure is based on duplication and works on complemented values in parallel. The chip was tested against side channel attacks showing the efficiency of the proposed countermeasure against such attacks. Fault injection tests based on the use of local laser shoots showed that the fault detection mechanism did indeed react as expected. However, using clock set-up time violations, 80% of the secret key were retrieved in less than 40 hours, thus illustrating the limits of the duplication countermeasure against a global fault attack which was published after the chip was designed.
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Contributor : Assia Tria <>
Submitted on : Wednesday, November 23, 2011 - 3:54:49 PM
Last modification on : Wednesday, June 24, 2020 - 4:18:31 PM


  • HAL Id : emse-00644114, version 1


Jacques Jean-Alain Fournier, Michel Agoyan, Sylvain Bouquet, Jean-Max Dutertre, Jean-Baptiste Rigaud, et al.. Design and characterisation of an AES chip embedding countermeasures. International Journal of Intelligent Engineering Informatics, 2011, 1 (3/4), pp.328-347. ⟨emse-00644114⟩



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