Investigation of timing constraints violation as a fault injection means

Abstract : Secure circuits are prone to a wide range of physical attacks. Among them, fault attacks are based on modifying the circuit environment in order to change its behaviour or to induce faults into its computations. As a result, the security level of the circuit under attack may be weaken. Many means are of common use to inject such faults: laser shot, electromagnetic pulse, overclocking, chip underpowering, temperature increase, etc. However, the mechanisms involved in the fault injection process have not been yet deeply investigate. Especially, those that have a global effect linked to timing constraints violation. In this paper we provide an experimental proof of the uniqueness of the fault injection process by means of the target's clock, power supply, or temperature alteration. We also studied further the properties of these fault injection means. These insights are intended to give designers guidelines to strengthen fault countermeasures. It also enable to imagine broad-spectrum countermeasures against most of the fault injection means.
Type de document :
Communication dans un congrès
27th Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2012, Avignon, France. pas encore paru, 2012
Liste complète des métadonnées

https://hal-emse.ccsd.cnrs.fr/emse-00742652
Contributeur : Hélène Le Bouder <>
Soumis le : mardi 16 octobre 2012 - 17:36:24
Dernière modification le : mercredi 14 février 2018 - 14:05:12

Identifiants

  • HAL Id : emse-00742652, version 1

Collections

Citation

Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson, Assia Tria. Investigation of timing constraints violation as a fault injection means. 27th Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2012, Avignon, France. pas encore paru, 2012. 〈emse-00742652〉

Partager

Métriques

Consultations de la notice

401