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Operand Folding Hardware Multipliers

Abstract : This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the partitions. The resulting design turns-out to be both compact and fast. When the operands' bit-length m is 1024, the new algorithm requires only 0.194m + 56 additions (on average), this is about half the number of additions required by the classical accumulate-and-add multiplication algorithm (m/2).
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Contributor : Hélène Le Bouder Connect in order to contact the contributor
Submitted on : Wednesday, October 17, 2012 - 11:03:00 AM
Last modification on : Thursday, May 26, 2022 - 3:55:15 AM

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Byungchun Chung, Amir Pasha Mirbaha, David Naccache, Sandra Marcello, Karim Sabeg. Operand Folding Hardware Multipliers. David Naccache. Cryptography and Security: From Theory to Applications:Essays Dedicated to Jean-Jacques Quisquater on the Occasion of His 65th Birthday, 6805, Springer, pp.319-328, 2012, LNCS - Lecture Notes in Computer Science, 978-3-642-28367-3. ⟨10.1007/978-3-642-28368-0_21⟩. ⟨emse-00742764⟩



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