Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells

Abstract : The use of a laser to inject faults into SRAM memory cells is well known. However, the corresponding fault model is often unknown or misunderstood: the induced faults may be described as bit-flip or bit-set/reset faults. We have investigated in this paper whether the bit-set/reset fault model or bit-flip fault model may be encountered in SRAMs. First, the fault model of a standalone SRAM was considered. Experiments revealed that the relevant fault model was the bit-set/reset. This result was further investigated through electrical simulations based on the use of an electrical model of MOS transistors under laser illumination. Then, fault injections have been performed on the RAM memory of a micro-controller to check the validity of the previous results based on experiments and simulations.
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Communication dans un congrès
Fault Diagnosis and Tolerance in Cryptography (FDTC), 2013 Workshop on, Aug 2013, Santa-Barbara, United States. 〈10.1109/FDTC.2013.17〉
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https://hal-emse.ccsd.cnrs.fr/emse-01109133
Contributeur : Jean-Max Dutertre <>
Soumis le : samedi 24 janvier 2015 - 18:01:42
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Cyril Roscian, Alexandre Sarafianos, Jean-Max Dutertre, Assia Tria. Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells. Fault Diagnosis and Tolerance in Cryptography (FDTC), 2013 Workshop on, Aug 2013, Santa-Barbara, United States. 〈10.1109/FDTC.2013.17〉. 〈emse-01109133〉

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