Differential Analysis of Round-Reduced AES Faulty Ciphertexts

Amir-Pasha Mirbaha 1 Jean-Max Dutertre 1 Assia Tria 2
1 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés
2 Laboratoire Systèmes et Architectures Sécurisés (LSAS)
SAS-ENSMSE - Département Systèmes et Architectures Sécurisés, CEA-TECH-Reg - CEA Tech en régions
Abstract : This paper describes new Round Reduction analysis attacks on an Advanced Encryption Standard (AES) implemen- tation by laser fault injection. The previous round reduction attacks require both of spatial and temporal accuracies in order to execute only one, two or nine rounds. We present new attacks by more flexible fault injection conditions. Our experiments are carried out on an 8-bit microcontroller which embeds a software AES with pre-calculated round keys. Faults are injected either into the round counter itself or into the reference of its total round number. The attacks may result to the use of a faulty round key at the last one or two executed rounds. The cryptanalysis of the obtained round-reduced faulty ciphertexts resorts to the differentiation techniques used by Differential Fault Analysis.
Keywords : AES algorithm Differential Fault Attack Round modification Attack
Type de document :
Communication dans un congrès
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, Oct 2013, New York, United States. 〈10.1109/DFT.2013.6653607〉
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Contributeur : Jean-Max Dutertre <>
Soumis le : samedi 24 janvier 2015 - 19:14:29
Dernière modification le : mardi 23 octobre 2018 - 14:36:11
Document(s) archivé(s) le : samedi 25 avril 2015 - 10:12:26

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Amir-Pasha Mirbaha, Jean-Max Dutertre, Assia Tria. Differential Analysis of Round-Reduced AES Faulty Ciphertexts. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, Oct 2013, New York, United States. 〈10.1109/DFT.2013.6653607〉. 〈emse-01109144〉

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