In semiconductor manufacturing, in-line inspections are necessary to monitor processes, products and tools in order to reduce excursions and achieve high yields of final products. However, capacity is limited and inspections directly impact the cycle times of products. Sampling strategies are used to improve product yields while limiting the number of inspections, and thus the impact on the cycle times of the inspected lots. Dynamic sampling has been recently introduced and new models are required to estimate the associated inspection capacity. In this paper, we focus on micro-defect inspections and the risk on process tools in terms of Wafers at Risk (W@R), which is the number of wafers processed on a tool since its latest defect inspection. A linear programming model that estimates the required defect inspection capacity to satisfy the W@R limits on process tools is proposed. Our model can be used at different decision levels. At the tactical level, it shows if W@R limits can be satisfied when the product mix changes and/or if planned W@R reductions can be met with the available inspection capacity. At the strategic level, the model helps to justify capacity investments if the objectives in terms of W@R reduction cannot be achieved with the available inspection capacity. Numerical experiments on industrial data are performed and discussed.