Xvpfloat: RISC-V ISA extension for variable extended precision floating point computation - Département Systèmes et Circuits Intégrés Numériques Access content directly
Journal Articles IEEE Transactions on Computers Year : 2024

Xvpfloat: RISC-V ISA extension for variable extended precision floating point computation

Abstract

In the field of scientific computation, numerical instability is a growing concern as the size of problems is continuously increasing. Numerical compensation techniques are a common solution, but are often problem specific, time consuming and require skilled numerical analysts. An alternative is to simply increase the working precision of the computation, but this is difficult due to the lack of efficient hardware support for extended precision. We propose Xvpfloat, a RISC-V ISA extension for dynamically variable and extended precision computation, a hardware implementation and a full software stack. Our architecture provides a comprehensive implementation of this ISA, with up to 512 bits of significand, including full support for common rounding modes and mixed precision arithmetic operations. The memory subsystem has full support for IEEE-754 extendable formats, and features specialized indexed loads and stores, and a prefetcher. This processor can either operate standalone or as an accelerator for a general purpose host. We demonstrate that the number of solver iterations can be reduced up to 5X and, for some problems, convergence is only possible with very high precision (384-bits). This accelerator provides a new approach to accelerate large scale scientific computing.
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Dates and versions

cea-04546949 , version 1 (15-04-2024)

Identifiers

Cite

Eric Guthmuller, César Fuguet, Andrea Bocco, Jérôme Fereyre, Riccardo Alidori, et al.. Xvpfloat: RISC-V ISA extension for variable extended precision floating point computation. IEEE Transactions on Computers, 2024, pp.1-14. ⟨10.1109/TC.2024.3383964⟩. ⟨cea-04546949⟩
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