When Clocks Fail: On Critical Paths and Clock Faults
Abstract
Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order. This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles. We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack).
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HAL_CARDIS2010_When_Clocks_Fail_On_Critical_Paths_And_Clock_Faults.pdf (576.02 Ko)
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