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Conference papers
When Clocks Fail: On Critical Paths and Clock Faults
Abstract : Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order. This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles. We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack).
Cited literature [16 references]
https://hal-emse.ccsd.cnrs.fr/emse-00474337
Contributor : Jean-Max Dutertre <>
Submitted on : Thursday, March 19, 2015 - 1:48:22 PM
Last modification on : Wednesday, June 24, 2020 - 4:18:22 PM
Document(s) archivé(s) le : Monday, April 17, 2017 - 6:39:00 PM
Contributor : Jean-Max Dutertre <>
Submitted on : Thursday, March 19, 2015 - 1:48:22 PM
Last modification on : Wednesday, June 24, 2020 - 4:18:22 PM
Document(s) archivé(s) le : Monday, April 17, 2017 - 6:39:00 PM
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