When Clocks Fail: On Critical Paths and Clock Faults

Michel Agoyan 1 Jean-Max Dutertre 2 David Naccache 3 Bruno Robisson 1 Assia Tria 1
1 ERC CEA / EMSE - Équipe de Recherche Commune CEA - EMSE (SESAM : Secured Embedded Systems And Microelectronics)
2 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés
3 LIENS - Laboratoire d'informatique de l'école normale supérieure
Abstract : Whilst clock fault attacks are known to be a serious security threat, an in-depth explanation of such faults still seems to be put in order. This work provides a theoretical analysis, backed by practical experiments, explaining when and how clock faults occur. Understanding and modeling the chain of events following a transient clock alteration allows to accurately predict faulty circuit behavior. A prediction fully confirmed by injecting variable-duration faults at predetermined clock cycles. We illustrate the process by successfully attacking an fpga aes implementation using a dll-based fpga platform (one-bit fault attack).
Keywords : differential fault attack delay locked loop clock modification fault attack AES clock glitch
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Communication dans un congrès
Springer Verlag. 9th IFIP WG 8.1/11.2 International conference, CARDIS 2010, Apr 2010, Passau, Germany. Springer Verlag, pp.182-193, 2010, Lecture Notes in Computer Science. 〈10.1007/978-3-642-12510-2_13〉
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Contributeur : Jean-Max Dutertre <>
Soumis le : jeudi 19 mars 2015 - 13:48:22
Dernière modification le : mardi 24 avril 2018 - 17:20:10
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Michel Agoyan, Jean-Max Dutertre, David Naccache, Bruno Robisson, Assia Tria. When Clocks Fail: On Critical Paths and Clock Faults. Springer Verlag. 9th IFIP WG 8.1/11.2 International conference, CARDIS 2010, Apr 2010, Passau, Germany. Springer Verlag, pp.182-193, 2010, Lecture Notes in Computer Science. 〈10.1007/978-3-642-12510-2_13〉. 〈emse-00474337〉

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