Material Emulation of Faults on Cryptoprocessors
Résumé
This paper describes a block that can be added to a crypto-processor embedded on a FPGA. This block enables to simulate the co- processor behaviour when faults are injected. Three fault models are used and an example with AES is given. The aim of such a block is to speed up the test of countermeasures on a FPGA before running the chip in fab.
| Origine | Fichiers produits par l'(les) auteur(s) |
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