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Conference papers
Material Emulation of Faults on Cryptoprocessors
Abstract : This paper describes a block that can be added to a crypto-processor embedded on a FPGA. This block enables to simulate the co- processor behaviour when faults are injected. Three fault models are used and an example with AES is given. The aim of such a block is to speed up the test of countermeasures on a FPGA before running the chip in fab.
Cited literature [4 references]
https://hal-emse.ccsd.cnrs.fr/emse-00494246
Contributor : Jean-Baptiste Rigaud <>
Submitted on : Tuesday, June 22, 2010 - 2:59:29 PM
Last modification on : Wednesday, June 24, 2020 - 4:18:32 PM
Long-term archiving on: : Friday, September 24, 2010 - 5:47:12 PM
Contributor : Jean-Baptiste Rigaud <>
Submitted on : Tuesday, June 22, 2010 - 2:59:29 PM
Last modification on : Wednesday, June 24, 2020 - 4:18:32 PM
Long-term archiving on: : Friday, September 24, 2010 - 5:47:12 PM
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SAME2006.pdf
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