A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values

Abstract : A secure AES chip was implemented in HCMOS9gp 130nm STM technology. The counter-measures are based on duplication (for detecting faults) and working on complemented values in parallel. The chip was tested against side-channel and fault attacks and resisted to both, thus illustrating the efficiency of our approach.
Type de document :
Communication dans un congrès
International Solid State Circuits Conference - ISSCC 2011, Feb 2011, San Francisco, United States. pp.15.6, 2012
Liste complète des métadonnées

https://hal-emse.ccsd.cnrs.fr/emse-00541009
Contributeur : Jacques Jean-Alain Fournier <>
Soumis le : lundi 29 novembre 2010 - 16:08:32
Dernière modification le : mercredi 29 novembre 2017 - 15:14:30

Identifiants

  • HAL Id : emse-00541009, version 1

Collections

Citation

Jacques Jean-Alain Fournier, Doulcier Marion, Jean-Max Dutertre, Jean-Baptiste Rigaud, Bruno Robisson, et al.. A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values. International Solid State Circuits Conference - ISSCC 2011, Feb 2011, San Francisco, United States. pp.15.6, 2012. 〈emse-00541009〉

Partager

Métriques

Consultations de la notice

296