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Communication Dans Un Congrès Année : 2012

A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values

Résumé

A secure AES chip was implemented in HCMOS9gp 130nm STM technology. The counter-measures are based on duplication (for detecting faults) and working on complemented values in parallel. The chip was tested against side-channel and fault attacks and resisted to both, thus illustrating the efficiency of our approach.

Domaines

Cryptographie et sécurité [cs.CR]

Jacques Jean-Alain Fournier  : Connectez-vous pour contacter le contributeur

https://hal-emse.ccsd.cnrs.fr/emse-00541009

Soumis le : lundi 29 novembre 2010-16:08:32

Dernière modification le : mercredi 1 mars 2023-05:03:10

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Dates et versions

emse-00541009 , version 1 (29-11-2010)

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Citer

Jacques Jean-Alain Fournier, Marion Doulcier, Jean-Max Dutertre, Jean-Baptiste Rigaud, Bruno Robisson, et al.. A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values. ISSCC 2011 - International Solid State Circuits Conference, Feb 2011, San Francisco, United States. pp.274-276, ⟨10.1109/ISSCC.2011.5746316⟩. ⟨emse-00541009⟩

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