Dispatching of Lots to Dynamically Reduce the Wafers at Risk in Semiconductor Manufacturing

Abstract : This paper presents a lot dispatching strategy to reduce the Wafer at Risk (W@R) on process tools, i.e. the number of wafers processed between two defectivity inspections. Due to the highly complex manufacturing process and the molecular scope of operations, defectivity inspections are critical for sustaining high yield levels of products. The novel dispatching strategy guides operators in selecting lots that will later be controlled in defectivity. Results show that the system is effective since the impact of measures has improved and the Wafer at Risk on process tools has been reduced
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Communication dans un congrès
8th IEEE International conference on Automation Science and Engineering, Aug 2012, Seoul, South Korea. pp.1-4, 2012
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https://hal-emse.ccsd.cnrs.fr/emse-00722672
Contributeur : Gloria Luz Rodriguez Verjan <>
Soumis le : vendredi 3 août 2012 - 08:49:18
Dernière modification le : mercredi 29 novembre 2017 - 10:06:23

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  • HAL Id : emse-00722672, version 1

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Gloria Luz Rodriguez Verjan, Eric Tartiere, Jacques Pinaton, Stéphane Dauzère-Pérès, Alexis Thieullen. Dispatching of Lots to Dynamically Reduce the Wafers at Risk in Semiconductor Manufacturing. 8th IEEE International conference on Automation Science and Engineering, Aug 2012, Seoul, South Korea. pp.1-4, 2012. 〈emse-00722672〉

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