Dispatching of Lots to Dynamically Reduce the Wafers at Risk in Semiconductor Manufacturing - Mines Saint-Étienne Access content directly
Conference Papers Year : 2012

Dispatching of Lots to Dynamically Reduce the Wafers at Risk in Semiconductor Manufacturing

Abstract

This paper presents a lot dispatching strategy to reduce the Wafer at Risk (W@R) on process tools, i.e. the number of wafers processed between two defectivity inspections. Due to the highly complex manufacturing process and the molecular scope of operations, defectivity inspections are critical for sustaining high yield levels of products. The novel dispatching strategy guides operators in selecting lots that will later be controlled in defectivity. Results show that the system is effective since the impact of measures has improved and the Wafer at Risk on process tools has been reduced
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Dates and versions

emse-00722672 , version 1 (03-08-2012)

Identifiers

  • HAL Id : emse-00722672 , version 1

Cite

Gloria Luz Rodriguez Verjan, Eric Tartiere, Jacques Pinaton, Stéphane Dauzère-Pérès, Alexis Thieullen. Dispatching of Lots to Dynamically Reduce the Wafers at Risk in Semiconductor Manufacturing. 8th IEEE International conference on Automation Science and Engineering, Aug 2012, Seoul, South Korea. pp.1-4. ⟨emse-00722672⟩
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