Laser attacks on integrated circuits: from CMOS to FD-SOI

Jean-Max Dutertre 1 Stephan De Castro 1, 2 Alexandre Sarafianos 3 Noémie Boher 4, 3 Bruno Rouzeyre 5 Mathieu Lisart 3 Joel Damiens 3 Philippe Candelier 3 Marie-Lise Flottes 5 Giorgio Di Natale 5
1 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 ST-TOURS - STMicroelectronics [Tours]
4 LCIS - Laboratoire de Conception et d'Intégration des Systèmes
5 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model permitted us to draw the laser sensitivity map of a SRAM cell. It demonstrates a very close correlation with experimental measures. We also introduce the preliminary results we gathered to build a similar electrical model for FD-SOI circuits. FD-SOI technology is expected to be less sensitive to laser than CMOS.
Keywords : fault attack Laser fault injection FD-SOI CMOS electrical model
Type de document :
Communication dans un congrès
DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014, 〈10.1109/DTIS.2014.6850664〉
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Soumis le : mercredi 7 janvier 2015 - 14:37:29
Dernière modification le : jeudi 7 février 2019 - 14:22:54
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Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, et al.. Laser attacks on integrated circuits: from CMOS to FD-SOI. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014, 〈10.1109/DTIS.2014.6850664〉. 〈emse-01099042〉

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