Power supply glitch induced faults on FPGA: an in-depth analysis of the injection mechanism

Abstract : Secure circuits are prone to a wide range of physical attacks. Among those are fault attacks based on modifying the circuit environment in order to change its behaviour or to induce faults into its computations. There are many common means used to inject such faults: laser shots, electromagnetic pulses, overclocking, chip underpowering, temperature increase, etc. In this paper we study the effect of negative power supply glitches on a FPGA. The obtained faults were compared to faults injected by clock glitches. As a result, both power and clock glitch induced faults were found to be identical. Because clock glitches are related to timing constraint violations, we shall consider that both power and clock glitches share this common fault injection mechanism. We also further studied the properties of this fault injection means.
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Communication dans un congrès
On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International, Jul 2013, Chania, Greece. 〈10.1109/IOLTS.2013.6604060〉
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https://hal-emse.ccsd.cnrs.fr/emse-01109131
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Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Assia Tria. Power supply glitch induced faults on FPGA: an in-depth analysis of the injection mechanism. On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International, Jul 2013, Chania, Greece. 〈10.1109/IOLTS.2013.6604060〉. 〈emse-01109131〉

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