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Conference Papers Year : 2013

From physical stresses to timing constraints violation

Abstract

Secure circuits are prone to a wide range of physical attacks. Among those are fault attacks based on modifying the circuit environment in order to change its behaviour or to induce faults into its com- putations. As a result, the security level of the circuit under attack may be weakened. There are many common means used to inject such faults: laser shots, electromagnetic pulses, overclocking, chip underpowering, temperature increase, etc. In this paper we describe how negative power supply glitches may be used to create timing constraint violations. The obtained faults were studied and compared to faults injected by clock glitches. Both power and clock glitch induced faults were found to be identical. Because clock glitches are related to timing constraint viola- tions, we shall consider that both power and clock glitches share this common fault injection mechanism. We also further studied the prop- erties of this fault injection means. These insights are intended to give guidelines to designers in order to strengthen fault countermeasures.
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Dates and versions

emse-01110353 , version 1 (28-01-2015)

Identifiers

  • HAL Id : emse-01110353 , version 1

Cite

Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Assia Tria. From physical stresses to timing constraints violation. Forth International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2013, Mar 2013, Paris, France. ⟨emse-01110353⟩
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