Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology

A Sarafianos 1 R Llido 1, 2 O Gagliano 1 V Serradeil 1 Mathieu Lisart 1 V. Goubier 1 Jean-Max Dutertre 3 Assia Tria 4 Vincent Pouget 2 Dean Lewis 2
1 ST-TOURS - STMicroelectronics [Tours]
2 IMS - Laboratoire de l'intégration, du matériau au système
3 SAS-ENSMSE - Département Systèmes et Architectures Sécurisés
4 Laboratoire Systèmes et Architectures Sécurisés (LSAS)
SAS-ENSMSE - Département Systèmes et Architectures Sécurisés, CEA-TECH-Reg - CEA Tech en régions
Abstract : This paper presents the electrical model of an NMOS transistor in 90nm technology under 1064nm Photoelectric Laser Stimulation. The model was built and tuned from measurements made on test structures and from the results of physical simulation using Finite Element Modeling (TCAD). The latter is a useful tool in order to understand and correlate the effects seen by measurement by given a physical insight of carrier generation and transport in devices. This electrical model enables to simulate the effect of a continuous laser wave on an NMOS transistor by taking into account the laser's parameters (i.e. spot size and power), spatial parameters (i.e. the spot location and the NMOS' geometry) and the NMOS' bias. It offers a significant gain of time for experiment processes and makes it possible to build 3D photocurrent cartographies generated by the laser on the NMOS, in order to predict its response independently of the laser beam location.
Keywords : Photoelectric Laser Stimulation
Type de document :
Communication dans un congrès
38th International Symposium for Testing and Failure Analysis, ISTFA 2012, Nov 2012, Phoenix, United States
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Contributeur : Jean-Max Dutertre <>
Soumis le : jeudi 12 mars 2015 - 10:13:14
Dernière modification le : mardi 23 octobre 2018 - 14:36:11
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A Sarafianos, R Llido, O Gagliano, V Serradeil, Mathieu Lisart, et al.. Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology. 38th International Symposium for Testing and Failure Analysis, ISTFA 2012, Nov 2012, Phoenix, United States. 〈emse-01130636〉

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