The behaviour of Integrated Circuits (IC), in Space, the high atmosphere or even in earth environment, are adversely affected by radiation. One of the most concerning effect is stochastic, caused by heavy ions of high energy which cannot be shielded. Striking the circuits, the invasive particles induce transient current upsets, being the cause of unpredictable soft errors in combinatorial logic and memory cells. After a brief survey of the phenomenon and its consequences, we report a strategy to improve the hardening capabilities of a standard commercial technology only using a design methodology. We present a new inverter architecture for which robustness is naturally attained during upset. The hardening is carried out through the use of an integrated information redundancy and a double tri-state output. The design prevents errors to propagate and gives an uncorrupted information source. Post layout SPICE simulations of the cells confirm the efficiency of our integrated approach to avoid the induced effect of a pulse shape current generation inside the IC.