Integrated Evaluation Platform for Secured Devices
Abstract
In this paper, we describe the structure of a FPGA
smart card emulator. The aim of such an emulator is to improve
the behaviour of the whole architecture when faults occur. Within
this card, an embedded Advanced Encryption Standard (AES)
protected against DFA is inserted as well as a fault injection
block. We also present the microprocessor core which controls
the whole card.
| Origin | Files produced by the author(s) |
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