Practical measurements of data path delays for IP authentication & integrity verification

Abstract : This paper describes the results of the practical measurements done to determine the path delay associated with each bit of a hardware AES FPGA implementation using a clock glitch injection tool. We illustrate how the measured path delays can constitute a characteristic fingerprint of an Intellectuel Property (IP) and can be used to detect the insertion of hardware trojans. The influence of synthesis options and inter die variations on the measurements is also studied. Compared to trojan detection schemes based on path delay characterisations already proposed in the literature, our approach does not require any additional test circuit to be inserted in the IP. Moreover our results are based on practical measurements.
Type de document :
Poster
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on, Jul 2013, Darmstadt, Germany. 〈10.1109/ReCoSoC.2013.6581551〉
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https://hal-emse.ccsd.cnrs.fr/emse-01109140
Contributeur : Jean-Max Dutertre <>
Soumis le : samedi 24 janvier 2015 - 18:53:50
Dernière modification le : vendredi 11 septembre 2015 - 10:00:08
Document(s) archivé(s) le : samedi 25 avril 2015 - 10:12:08

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Ingrid Exurville, Jacques Fournier, Jean-Max Dutertre, Bruno Robisson, Assia Tria. Practical measurements of data path delays for IP authentication & integrity verification. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on, Jul 2013, Darmstadt, Germany. 〈10.1109/ReCoSoC.2013.6581551〉. 〈emse-01109140〉

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