SEU sensitivity and modeling using picosecond pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology - Mines Saint-Étienne Access content directly
Conference Papers Year : 2015

SEU sensitivity and modeling using picosecond pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

Abstract

—This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).
Fichier principal
Vignette du fichier
hal_DFTS_2015_SEU_sensitivity_and_modeling_using_picosecond_pulsed_laser_stimulation_of_a_D_Flip_Flop_in_40_nm_CMOS_technology.pdf (2.18 Mo) Télécharger le fichier
P_2015_4_Champeix_Clement_DFTS2015_slides.pdf (2.53 Mo) Télécharger le fichier
Origin : Files produced by the author(s)
Origin : Files produced by the author(s)
Loading...

Dates and versions

emse-01227355 , version 1 (10-11-2015)
emse-01227355 , version 2 (17-11-2015)

Identifiers

Cite

Clément Champeix, Nicolas Borrel, Jean-Max Dutertre, Bruno Robisson, Mathieu Lisart, et al.. SEU sensitivity and modeling using picosecond pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on, Oct 2015, Amherst, United States. ⟨10.1109/DFT.2015.7315158⟩. ⟨emse-01227355v2⟩
378 View
846 Download

Altmetric

Share

Gmail Facebook X LinkedIn More